1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device using a laser irradiation apparatus for irradiating an object with a laser beam. Specifically, the present invention relates to a semiconductor device including a thin film transistor (hereinafter referred to as a TFT) having ultrashallow junction. For example, the present invention relates to a large scale integrated circuit (LSI), an electro-optic device typified by a liquid crystal display panel, a light-emitting display device having a light-emitting element, a light-receiving device having a CCD (charge-coupled device), a memory device such as an SRAM or a DRAM, and an electronic appliance equipped with any one of these devices as its component.
In this specification, the semiconductor device indicates general devices which can function by using a semiconductor characteristic. An electro-optic device, a semiconductor circuit, and an electronic appliance having these are all included in the semiconductor device.
2. Related Art
Research and development have been widely conducted on size reduction and high integration of semiconductor elements. In particular, a technique for reducing the size of an insulating gate electric-field effect semiconductor element called a MOSFET (MOS Field Effect Transistor) has been remarkably advanced. MOS stands for Metal-Oxide-Semiconductor, which is a structure in which three kinds of materials (substances) of metal, oxide, and semiconductor are combined.
Here, the metal includes not only pure metal but also a semiconductor material having sufficiently high conductance, an alloy of semiconductor and metal, and the like. The oxide includes not only pure oxide but also an insulating material having sufficiently high resistance, such as nitride. Even in such cases, the term MOS is applied in general. Hereinafter in this specification, an electric-field effect element having such a structure including nitride and other insulating materials is referred to as a MOSFET.
Either an N-channel or P-channel MOSFET generally includes a channel formation region, a gate insulating film, a gate electrode, a source region, and a drain region. Since this MOSFET can be highly-integrated easily, the MOSFET is widely used as a transistor element having an integrated circuit.
A MOSFET is reduced in size by narrowing the width of its gate electrode. With the size reduction of a MOSFET, an LDD (Lightly Doped Drain) structure in which a drain region on a channel formation region side is lightly doped as shown in FIG. 2F is used to prevent a short-channel effect or hot electron generation.
By employing the LDD structure, the amount of impurities diffusing into the drain region on the channel formation region side can be decreased and the length of a channel length can be secured. Moreover, since the gradient of impurity concentration distribution in a pn junction portion formed at a boundary between a channel formation region and an impurity region (drain region) can be relaxed, electric-field concentration can be relaxed in this region, which allows stabilization of operation of an element.
A MOSFET having an LDD structure is formed as shown in FIGS. 2A to 2F in general. Although an example of manufacturing an N-type MOSFET is shown here, a P-type MOSFET can also be manufactured similarly.
First, an oxide film 201 and a conductive film 202 are formed over a main plane of a P-type semiconductor substrate 200 as shown in FIG. 2A. By etching these films, a gate insulating film 203 and a gate electrode 204 are formed respectively as shown in FIG. 2B. Then, an impurity is introduced into the main plane of the semiconductor substrate by an ion implantation method or the like by using the gate electrode 204 as a mask, thereby forming a low-concentration impurity region 205 in a self-aligning manner (this impurity region is hereinafter referred to as an extension region) (FIG. 2C). In this case, the extension region 205 is shown with an n− mark.
Next, as shown in FIG. 2D, an insulating film 206 is formed over the extension region 205. Then, anisotropic etching such as bias plasma etching is conducted to the insulating film 206, thereby forming a sidewall spacer 207 (FIG. 2E). Next, a high-concentration impurity region (shown with an n+ mark) is formed in a self-aligning manner by using the sidewall spacer 207 as a mask. After that, the added impurity is activated by heating the respective impurity regions so that a source region 208 and a drain region 209 are formed (FIG. 2F).
Further size reduction is required also in a MOSFET. The problem is, however, the decrease in drain current. In order to solve this, it is effective to make an extension region low resistant. In order to lower the resistance of the extension region, ions of impurities need to be implanted at high concentration into an ultrashallow region of a main plane of a semiconductor substrate and the implanted impurities need to be activated.
Conventionally, an RTA (Rapid Thermal Annealing) method has been employed as a heat treatment for activating an impurity. However, this RTA has the following problem.
In an RTA method, heat time is as long as several seconds during which an impurity inside an extension region diffuses deep. When the impurity diffuses deep, junction becomes deep, resulting in that an area where a gate electrode overlaps a source region and a drain region becomes larger. Therefore, the effective channel length becomes shorter, which causes electric-field concentration and a short-channel effect. Consequently, a novel annealing method which can carry out a heat treatment in a shorter time than the heat treatment by RTA is required.